1. Field of the Invention
Embodiments of the invention relate to the field of device manufacturing. More particularly, the present invention relates to a method, system and structure for patterning a substrate for manufacturing a device.
2. Discussion of Related Art
In forming electronic devices, patterning processes are widely used. As known in the art, there exist various types of patterning processes. One example of the process is a photolithographic patterning process by which a pattern of desired resolution is transferred optically from an optical mask to a photoresist layer deposited onto the substrate and, ultimately, to the substrate. In one example, patterning has been used on a substrate to form the gate of a field effect transistor.
With continuing miniaturization of electronic devices, there is an increased need for a patterning process capable of achieving finer resolution. However, limitations in forming a mask with a desired resolution and having compatibility with the properties (e.g. wavelength) of the radiation used in the patterning process have led to difficulties in achieving patterns with the desired resolution. To overcome such difficulties, several techniques have been proposed. One of such techniques proposes using an electron beam to write the pattern directly onto the photoresist without using a mask. Although the technique is capable of forming the patterns with fine resolution, the process is very time consuming and costly. Other techniques propose using soft x-rays or extreme UV radiation, both examples of radiation with shorter wavelength than the currently used UV wavelengths, in order to form the mask having desired pattern resolution and/or to transfer the pattern from the mask to the photoresist layer. However, soft x-rays or extreme UV radiation are difficult to manipulate using mirrors and/or optical lenses. In addition, using soft x-rays or extreme UV radiation to pattern a substrate may have undesirable optical effects (e.g. self-interference) and may affect the definition of the pattern of the photoresist layer, thus adversely affecting the resolution of the patterned substrate.
Other techniques that are proposed to address the need for improved patterning processes include a self-aligned double patterning lithographic (SADPL) process. Referring to FIGS. 1a-k, there is shown a conventional SADPL process performed on a substrate 101 for forming gates of transistors. Each of FIGS. 1a-1k is a schematic cross-section of a substrate having a known stack of patterning layers designed for self-aligned double patterning. As illustrated in FIG. 1a, the substrate 101 may comprise silicon wafer 102, an oxide layer 104, and a polysilicon or metal layer 106.
A layer of hard mask film 108 may be deposited onto the substrate 108. On top of the hard mask film 101, a first amorphous carbon layer (ACL) film 110 may be deposited. Thereafter, a first SiON film 112 may be deposited. A second ACL film 114 may be deposited on the first SiON film 112. On the second ACL film 114, a second SiON film 116 may be deposited. Thereafter, a layer of photoresist film 118 may be deposited. After depositing the photoresist film 118, a primary lithographic process may be performed to pattern the photoresist film 118. As illustrated in FIG. 1a, the primary lithographic process may result in a patterned photoresist structure that comprises an array of islands separated from one another by gaps having a first width 120a. Islands 118 depict idealized cross-sections of patterned resist features, which may, in plan view, have the shape of elongated “lines,” rectangles, squares, or other shapes. Moreover, islands 118 are typically arranged in an array having many such islands that are arranged similarly to those depicted in FIG. 1a. 
Referring to FIG. 1b, the patterned photoresist islands may be trimmed via an etch trim process. As a result, the width of the gaps may be enlarged to a second width 120b and the feature size of the patterned photoresist islands may be adjusted to a desired feature size. Referring to FIG. 1c, the second SiON film 116 may then be etched so as to transfer the pattern of the patterned photoresist islands 118 to the second SiON film 116. Thereafter, the patterned photoresist islands 118 may be removed from the second SiON film 116 as illustrated in FIG. 1c. 
Following the removal of the patterned photoresist islands 118 from the second SiON film 116, the second ACL film 114 may be etched, and the pattern of the second SiON film 116 may be transferred to the second ACL film 114 (FIG. 1e). Referring to FIG. 1f, the second SiON film 116 may be removed. After removing the second SiON film 116 from the patterned second ACL film 114, a layer of spacer film 122 may be deposited on to the patterned second ACL film 114 and the first SiON film 112 (FIG. 1g). A blanket etchback process may be performed to the layer of spacer film 122, resulting in spacers 122 disposed along the sidewall of the patterned second ACL film 114 (FIG. 1h).
The patterned second ACL film 114 may then be removed (FIG. 1i), and the first SiON film 112 and the first ACL film 110 may be etched (FIG. 1j) to form columns separated from one another by gaps having a third width 120c. Thereafter, the hard mask layer 108 and the poly or metal gate layer 106 of the substrate 101 may be etched so as to transfer the pattern the columns shown in FIG. 1j. The hard mask layer 108 is subsequently removed from the poly or metal gate layer 106, and a patterned substrate 101 having the poly or metal gate layer 106 of desired feature size may be formed, as depicted in FIG. 1k. 
The conventional SADPL method, although adequate, has several shortcomings. For example, the etch trim process used in the conventional SADPL process to trim the patterned photoresist 118 may not be precise and may be difficult to control. In addition, the conventional SADPL process requires multiple deposition steps to deposit multiple layers of ACL and SiON films and multiple etching steps to etch the films. The technique, therefore, is costly and inefficient. Such inefficient processes may place undue financial burden on the manufacturers of the devices and, ultimately, the consumers. Accordingly, new techniques for patterning a substrate are needed.